The Impact of Soft Error on C-Elements Due to Process Corner Variation and Temperature

  • Norhuzaimin Julai Department of Electrical and Electronics, Universiti Malaysia Sarawak, Kota Samarahan
Keywords: Soft Error, Process Variation, Temperature.


This paper presents current injection resemble single event upset (SEU) current at the vulnerable nodes on different configurations of C-elements under two different scenarios: process corner and temperature. The objectives are to identify the vulnerable nodes due to SEU and to find the critical charges needed to flip the output from low to high (0-1) and high to low (1-0) on different configurations of C-elements. The comparisons of C-elements in term of the resistivity toward soft error are presented.


Rajaraman Ramanarayanan, Ramakrishnan Krishnan, Vijaykrishnan Narayanan and Mary Jane Irwin, Modelling Soft Errors at the Device and Logic Levels for Combinational Circuits, IEEE Transactions on Dependable and Secure Computing, Vol 6, No 3, 2009.

Fan Wang and Vishwani D. Agrawal, Single Event Upset: An Embedded Tutorial, 21st International Conference on VLSI Design, 2008, pp 429 - 434.

Anghel, M.Rebaunger, M.Sonze Reorda and M.Violante, Multi-Level Fault Effects Evaluation, Radiation Effects on Embedded Systems,Springer, 2007, pp. 69-88

Gottfried Fuchs, Matthias Fugger and Andreas Steininger, On the Threat of Metastability in an Asynchronous Fault-Tolerant Clock Generation Scheme, Fault-Tolerant Distributed Algorithms on VLSI Chips

Weidong Kuang, Ibarra C.M and Peiyi Zhao, Soft Error Hardening for Asynchronous Circuits ,22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2007, pp 273-281.

Hungse Cha and Janak H. Patel, A Logic Level Model for Alpha Particle Hits in CMOS Circuits, International Conference on Computer Design, October 1993, pp 538-542.

V.A. Carreno and G Choi, R.K Layer, Analog-Digital Simulation of Transient-Induced Logic Errors and Upset Susceptibility of an Advanced Control System, NASA Technical Memorondum 4241, Nov 1990.

A. J. Martin, Formal Program Transformations for VLSI Circuit Synthesis, Formal Development of Programs and Proofs (E. W. Dijkstra, ed.), UT Year of Program- ming Series, pp. 59-80, Addison-Wesley, 1989

I. E. Sutherland, Micropipelines, Communications of the AGM, Vol. 32, pp. 720-738, June 1989

K. van Berkel, Beware the Isochronic Fork, The VLSI journal, Vol. 13, pp. 103-128, June 1992

Tino Heijmen et al, A Comparative Study on the Soft-Error Rate of Flip-Flop from 90-nm production Libraries, 44th IEEE International Symposium on Reliability Physics, March 2006, pp. 204-211.

Kumar, R and Kursun, V, Impact of Temperature Fluctuation on Circuits Characteristics in 180nm and 65 nm CMOS Technologies, International Symposium on Circuits and Systems, 2006, pp. 3858-3861.

How to Cite
Julai, N. (2015). The Impact of Soft Error on C-Elements Due to Process Corner Variation and Temperature. Journal of Applied Science & Process Engineering, 2(2), 83-96.