Design and Optimization of Low Drop-Out (LDO) Voltage Regulator in 180nm CMOS Technology
DOI:
https://doi.org/10.33736/jese.14063.2026Keywords:
Low-Dropout Regulator, CMOS LDO, PMOS Pass Transistor, Two-Stage OTA, Power Supply Rejection Ratio (PSRR).Abstract
Low-dropout (LDO) voltage regulators are widely used in low-power electronic systems to provide a stable supply voltage while minimizing voltage headroom and power consumption. This paper presents the design and optimization of a capacitorless Low-Dropout (LDO) Voltage Regulator implemented in a 0.18 μm CMOS technology. The proposed architecture utilizes a conventional two-stage operational transconductance amplifier (OTA) with standard Miller compensation and a PMOS pass device to achieve area-efficient voltage regulation for always-on intermediate-load electronic devices. Operating from an input supply of 2.0 V to 3.3 V, the LDO delivers a stable 1.8 V output with a low dropout voltage of 100 mV at a maximum load of 10 mA. The design is specifically optimized for systems maintaining a minimum continuous load of 1 mA, under which it achieves a phase margin of >60°. Simulation results demonstrate a unity-gain frequency (UGF) of 593 kHz, a nominal quiescent current of 198 μA, and a worst-case high-frequency Power Supply Rejection Ratio (PSRR) of 46.78 dB. Comprehensive PVT corner analysis confirms robust regulation across variations, making this architecture highly suitable for reliable, intermediate-current sensor nodes and analog sub-circuits.
References
References
Ejjagiri, V. G., Dilna, U., Shashikala, V., & Reddy, B. (2023). Design of stable 3.3 V to 1.8 V, 100 mA low drop out voltage regulator using 180 nm technology. In Proceedings of the 14th International Conference on Computing, Communication and Networking Technologies (ICCCNT), 1–5.
Gray, P. R., & Meyer, R. G. (1993). Analysis and design of analog integrated circuits. Wiley.
Wong, J. (1990). A low-noise low drop-out regulator for portable equipment. Power Conversion and Intelligent Motion, 38–43.
Ismail, M., & Fiez, T. (1994). Analog VLSI: Signal and information processing. McGraw-Hill.
Goodenough, F. (1995, September 5). Fast LDOs and switchers provide sub-5-V power. Electronic Design, 43(18), 65–74.
Matsuzawa, A. (1993). Low voltage mixed analog/digital circuit design for portable equipment. In Proceedings of the IEEE Symposium on VLSI Circuits, 49–54.
Bhuiyan, M. A. S., Hossain, M. R., Minhad, K. N., Haque, F., Hemel, M. S. K., Dawi, O. M., Reaz, M. B. I., & Ooi, K. J. A. (2022). CMOS low-dropout voltage regulator design trends: An overview. Electronics, 11(2), 193. https://doi.org/10.3390/electronics11020193
Lin, H. C., Wu, H. H., & Chang, T. Y. (2008). An active-frequency compensation scheme for CMOS low-dropout regulators with transient-response improvement. IEEE Transactions on Circuits and Systems II: Express Briefs, 55(9), 853–857. https://doi.org/10.1109/TCSII.2008.924366
Saberkari, A., Alarcón, E., & Shokouhi, S. B. (2013). Fast transient current-steering CMOS LDO regulator based on current feedback amplifier. Integration, 46(2), 165–171. https://doi.org/10.1016/j.vlsi.2012.02.001
Chen, Y. P., & Tang, K. T. (2020). A fully integrated high-power-supply-rejection linear regulator with an output-supplied voltage reference. IEEE Transactions on Circuits and Systems I: Regular Papers, 67(11), 3828–3838. https://doi.org/10.1109/TCSI.2020.3008031
Widlar, R. J. (1971). New developments in IC voltage regulators. IEEE Journal of Solid-State Circuits, SC-6(1), 2–7.
Zachos, N., Gogolou, V., & Noulis, T. (2024). A fully integrated 1.8 V low-power LDO regulator with dynamic transient control for SoC applications. Electronics, 13(23), 4734. https://doi.org/10.3390/electronics13234734
Rincón-Mora, G. A., & Allen, P. E. (1998). A low-voltage, low quiescent current, low drop-out regulator. IEEE Journal of Solid-State Circuits, 33(1), 36–44.
Tan, J., & Sommer, R. (2019). Modeling of low-dropout regulator to optimize power supply rejection in system-on-chip applications. In Proceedings of the 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 113–116. https://doi.org/10.1109/SMACD.2019.8795239
Baharudin, S. N. S., Jambek, A. B., & Ismail, R. C. (2014). Design and analysis of a two-stage OTA for sensor interface circuit. In Proceedings of the IEEE Symposium on Computer Applications and Industrial Electronics (ISCAIE), 1–6. https://doi.org/10.1109/ISCAIE.2014.7010215
Allen, P. E., & Holberg, D. R. (2002). CMOS analog circuit design (2nd ed.). Oxford University Press.
Gupta, K. (2022). Design of a beta multiplier current reference circuit in 28 nm CMOS technology [GitHub repository]. GitHub. https://github.com/krishna-gup/beta-multiplier
Kay, M. (n.d.). Design and analysis of an LDO voltage regulator with a PMOS power device [Preliminary paper]. Texas Instruments.
Khan, M and Chowdhury, M. H. (2018). Capacitor-less Low-Dropout Regulator (LDO) with Improved PSRR and Enhanced Slew-Rate. In Proceedings of the 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence: 1–5. https://doi.org/10.1109/ISCAS.2018.8351039.
Giustolisi, G., Palumbo, G. and Spitale, E. (2007). LDO compensation strategy based on current buffer/amplifiers. In Proceedings of the 2007 18th European Conference on Circuit Theory and Design, Sevilla, Spain. 116–119. https://doi.org/10.1109/ECCTD.2007.4529550.
Patgar, R. R., Kotabagi, S. S., Javalagi, M. M, and Nasabi, S. (2025). Design and Performance Analysis of a Low Drop Out Voltage Regulator with High PSRR. In the Proceedings of 2025 IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI), Gwalior, India. 1–6. https://doi.org/10.1109/IATMSI64286.2025.10984897.
